The present invention relates to an operational amplifier that operates at low power-supply voltages. In particular, the present invention relates to a method and apparatus that includes a rail-to-rail input trans-conductance stage that supplies a current output to an output trans-conductance stage. The input and output stages operate over the full power supply range.
Differential amplifiers normal only operate over a limited range of input voltages. The maximum input voltage range for which a circuit continues to operate as an amplifier is termed the input common-mode range (CMR). When the input voltages (or common mode voltage) exceed the input CMR, transistors become cutoff, saturated, or breakdown in one or more gain stages of the amplifier. Typically, the CMR permits the common mode voltage (VCM) to approach within a few volts of either power supply voltage before the amplifier performance is degraded.
A simple differential amplifier (500) is shown in FIG. 5. As shown in the figure, a current source (IDIFF) sources a current into node 501. Transistor M51 has a source connected to node 501, a gate connected to an inverting input terminal (INN), and a drain connected to node 503. Transistor M52 has a source connected to node 501, a gate connected to a non-inverting input terminal (INP), and a drain connected to node 504. Transistor M53 is a diode-connected transistor with a gate and drain connected to node 503, and a source connected to VSS. Transistor M54 has a gate connected to node 503, a drain connected to node 504, and a source connected to VSS. Transistor M55 has a gate connected to node 504, a drain connected to an output terminal (VOUT), and a source connected to VSS. A second current source (IOUT) sources a current into the drain of transistor M55 (VOUT). A capacitor (CC) is connected between VOUT and node 103.
Transistors M51 and M52 are a matched pair of PMOS transistors that form a differential input stage of the differential amplifier (500). Transistors M53 and M54 form an NMOS current mirror, acting as a load for the differential input pair (M51, M52). Current source IDIFF supplies a xe2x80x9ctail currentxe2x80x9d to bias the differential input pair transistors into their active region of operation. NMOS transistor M55 serves as an amplifier, with an input at node 504 and an output at VOUT. The capacitor (CC) reduces the gain of the amplifier at high frequencies to provide a stable amplifier by Miller compensation.
The input differential pair transistors (M51, M52) limit the CMR of differential amplifier 500. Transistors M51 and M52 must be biased in saturation for the amplifier to function properly. A typical threshold voltage of a PMOS transistor (VTP) is on the order of xe2x88x921V. To remain in saturation, the source-to-gate voltage (VSG) of transistors M51 and M52 must be biased active (VSGxe2x89xa7|VTP|) Since the input differential pair transistors will be cutoff when VCM (the DC level at INM and INP) approaches the VDD power supply, the input differential pair transistors will operate as an amplifier when: VG51(max)=VG52(max)=VCM(max)xe2x89xa6VDDxe2x88x92|VTP|. The active load transistors (M53, M54), together with the input differential pair transistors (M51, M52) determine the minimum VCM for which the amplifier will operate properly. Transistors M51 and M52 must also have a source-to-drain voltage (VSD) that exceeds the saturation voltage (VSDxe2x89xa7VSGxe2x88x92|VTP|). The typical threshold voltage of a NMOS transistor (VTN) is on the order of +1V. The load transistors M53, M54 must be biased active (VGS53=VGS54 greater than VTN). The minimum VCM for amplifier 500, is determined by: VG51(min)=VG52(min)=VCM(min)xe2x89xa7VSS+VTNxe2x88x92|VTP|. Thus, amplifier 500 does not operate as a rail-to-rail amplifier.
The open loop gain of the amplifier (Av) is determined by the transconductance of transistors M52 and M55. The open loop gain of the amplifier (500) is on the order of 60 dB. The capacitor (CC) creates a dominant pole in the amplifier (500) such that the gain of the amplifier is reduced at high frequency. The unity-gain bandwidth (GBW) of the amplifier (500) is defined as the frequency where the gain drops from the open loop gain down to 0 dB. Since CC creates a dominant pole in the amplifier, the unity gain bandwidth (GBW) is proportional to gm/CC, where gm is the trans-conductance of the amplifier.
In accordance with the invention, the above and other problems are solved by an apparatus and method that is directed to an amplifier with a rail-to-rail output swing that operates on a very low power supply voltage.
Briefly stated, the present invention relates to a method and apparatus that is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors. The level shifting buffer amplifiers are also arranged such that the gate of each output transistor is selectively switched to a power supply voltage, providing maximum gate drive to the output transistor when the output transistor drives a maximum current to an external load. A single capacitor may be employed to provide compensation between the output of the amplifier and the output of the class AB turnaround stage. The sub-threshold operation of the level shifting buffer amplifiers permits the output stage amplifier to operate on power supplies down to roughly a single transistor threshold voltage.
According to a feature of the invention, a rail-to-rail output swing is achieved with a pair of MOS output transistors and a pair of corresponding drive level shifters that bias the output transistors for class AB operation and provide a maximum drive to the output transistors. In one example, the drive level shifters each include a sub-threshold biased MOS transistor operating as a resistive device that is used to generate an AB bias to one of the MOS output transistors.
According to another feature of the invention, drive level shifters in an output stage amplifier drive the gates of MOS output transistors over a maximum swing level such that maximum output current is available to an external load. In one example, the drive level shifters provide maximum gate drive to the MOS output transistors by coupling the gate to one of the power supply voltages.
According to still another feature of the invention, a single compensation capacitor provides high frequency compensation to an output stage amplifier that has a rail-to-rail output swing.
An embodiment of the invention is directed to an apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to an input signal at an input node. The apparatus includes a first active load device, that operates as a sub-threshold device, is coupled to the high power supply and a first intermediary node. A first diode device is coupled between the first intermediary node and a first drive node, wherein the first diode device is arranged to provide a high drive signal at the first drive node when active and the first diode device is inactive when the input signal is at the low potential. A first MOS transistor, wherein the gate of the first MOS transistor is coupled to a reference voltage, the drain of the first MOS transistor is coupled to the first drive node, and the source of the first MOS transistor is coupled to a first current source, wherein the first MOS transistor is arranged to couple the first drive node to the low potential when the first diode device is inactive. A second active load device, that operates as a sub-threshold device, is coupled to the low power supply and a second intermediary node. A second diode device is coupled between the second intermediary node and a second drive node, wherein the diode device is arranged to provide a low drive signal at the second drive node when active and the second diode device is inactive when the input signal is at the high potential. A second MOS transistor, wherein the gate of the second MOS transistor is coupled to the reference voltage, the drain of the second MOS transistor is coupled to the first drive node, and the source of the second MOS transistor is coupled to a second current source, wherein the second MOS transistor is arranged to couple the second drive node to the high potential when the second diode device is inactive. A class AB output drive circuit is arranged to provide the rail-to-rail output signal in response to the high drive signal and the low drive signal, wherein the class AB output drive circuit is biased for class AB operation.
Another embodiment of the invention is directed to an apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to a differential input signal. The apparatus includes an input stage amplifier circuit that produces a single-ended signal from the differential input signal, and an output stage amplifier circuit that produces the rail-to-rail output signal in response to the single-ended input signal. The output stage amplifier circuit includes a first active load device, that operates as a sub-threshold device, is coupled to the high power supply and a first intermediary node. A first diode device is coupled between the first intermediary node and a first drive node, wherein the first diode device is arranged to provide a high drive signal at the first drive node when active and the first diode device is inactive when the single-ended input signal is at the low potential. A first MOS transistor, wherein the gate of the first MOS transistor is coupled to the reference circuit, the drain of the first MOS transistor is coupled to the first drive node, and the source of the first MOS transistor is coupled to a first current source, wherein the first MOS transistor is arranged to couple the first drive node to the low potential when the first diode device is inactive. A second active load device, that operates as a sub-threshold device, is coupled to the low power supply and a second intermediary node. A second diode device is coupled between the second intermediary node and a second drive node, wherein the diode device is arranged to provide a low drive signal at the second drive node when active and the second diode device is inactive when the single-ended input signal is at the high potential. A second MOS transistor, wherein the gate of the second MOS transistor is coupled to the reference circuit, the drain of the second MOS transistor is coupled to the first drive node, and the source of the second MOS transistor is coupled to a second current source, wherein the second MOS transistor is arranged to couple the second drive node to the high potential when the second diode device is inactive. A class AB output drive circuit is arranged to provide the rail-to-rail output signal in response to the high drive signal and the low drive signal, wherein the class AB output drive circuit is biased for class AB operation.
Another embodiment of the invention is directed to an apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to an input signal at an input node. The apparatus includes a first means for level shifting that produces a first drive signal that corresponds to a first level shifted version of the input signal, the first means for level shifting providing gain between the input signal and the first drive signal, and the first means for level shifting is arranged to couple the first drive signal to the low potential when the potential of the input signal corresponds to the low potential. A second means for level shifting that produces a second drive signal that corresponds to a second level shifted version of the input signal, the second means for level shifting providing gain between the input signal and the second drive signal, and the second means for level shifting is arranged to couple the second drive signal to the high potential when the potential of the input signal corresponds to the high potential. A first output drive means is coupled to the output node, wherein the first output drive means is responsive to the first drive signal.
A second output drive means is coupled to the output node, wherein the second output drive means is responsive to the second drive signal, the first output drive means is arranged to cooperate with the second output drive means such that the first output drive means and the second output drive means provide the rail-to-rail output signal at the output node.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.